1. Field of the Invention
The invention relates in general to a triple-well structure for semiconductor integrated circuit (IC) devices and a process for its fabrication. In particular, the invention relates to the triple-well structural configuration for semiconductor IC devices formed in a P-type substrate for such devices and its process of fabrication.
2. Related Art
Semiconductor IC's can generally be categorized as either logic devices or memory devices. Logic devices include devices usually utilized to perform logical operations on digital information. For example, microprocessors employed as central processing units (CPUs) for computer systems are such logic devices, which are used to perform fast and complicated logical operations on digital data. On the other hand, memory devices include devices utilized to store digital information in various digital electronic systems. For example, random access memory (RAM) devices in a computer system are employed to temporarily hold data for the operation of the logic devices when required.
As the processing capability of microprocessors is becoming ever more powerful, the complexity and number of digital logic operations are also increasing. This explicitly translates into a need for increased data storage capacity in the memory devices employed in such digital electronics systems.
A significant majority of the semiconductor IC devices in use today are built around complementary metal-oxide semiconductor (CMOS) transistors. As the level of integration for semiconductor IC devices continues to increase, CMOS technology IC devices are becoming more and more popular due to their inherent suitability for high integration IC devices. There are three principle structural designs for CMOS transistors: Two of them are single-well designs that include N- and P-well designs, and a third, which is a double-well design uses twin P-wells.
The physical dimensions of the circuit elements in newly developed semiconductor IC devices are shrinking as such devices are being made with ever higher levels of integration. Once the physical resolution of the design of circuit elements is reduced to below about one micrometer (sub-micron), the electric field intensity in the channel region of a transistor increases due to the fact that the dimensions of that region have been reduced. The electric field intensity in the transistor channel region increases to a level where the operating characteristics of both N- and P-type MOS transistors become more and more similar. The design rules for state-of-the-art sub-micron semiconductor IC devices therefore regards complementary MOS transistors as the appropriate selection as components for the IC circuitry to be designed and fabricated.
Among the categories of memory devices, static random access memory (SRAM) is one of the fastest devices. Due to its necessarily fast access time cycles, SRAM is employed herein as an example to which the triple-well structural configuration and the process of fabrication of the invention may be applied. For purposes of comparison, an SRAM device having the conventional twin-well structure is examined briefly in FIGS. 1a-1c of the accompanying drawings.
FIGS. 1a-1c are cross-sectional views of a transistor in a conventional SRAM device having a twin-well structure, during respective selected stages of its fabrication. To construct such a twin-well transistor, the conventional process may be described to include the following process steps.
Step 1
Referring to FIG. 1a, an oxide layer 11 and a silicon nitride layer 12 are successively formed over the surface of an N-type silicon substrate 10.
Step 2
A photomask is then formed over the surface to define the active region in the silicon nitride layer 12 for the transistor to be fabricated. After the active region is formed, the photomask is removed.
Step 3
Silicon nitride layer 12 is then utilized as a shielding mask for the implementation of an ion implantation procedure to implant boron ions into the N-type substrate 10. The implantation may be performed at an energy level of about 200 KeV, and achieves an impurity dosage of about 1.times.10.sup.13 atoms/cm.sup.2.
Step 4
Another photomask is then formed for the purpose of implanting boron or phosphorous ions (not shown in the drawing) in the peripheral circuit regions to surround the P-type MOS transistor being fabricated for the SRAM device. At the conclusion of this ion implantation procedure, the photomask is removed.
Step 5
Referring next to FIG. 1b, a wet oxidation procedure is then employed to grow a field oxide layer 13, and is followed by a high-temperature thermal diffusion procedure that drives into the N-type substrate 10 the ions implanted in the previous Steps 3 and 4 in the N-type substrate 10. This forms a P-well 14 and N-wells not shown in the drawing.
Step 6
Next, the silicon nitride layer 12 is removed from the surface of the substrate.
Step 7
A further photomask is then employed to define the memory cell region for the SRAM device, after which a third ion implantation procedure is implemented. In this implantation procedure boron ions are implanted in the defined memory cell region. The boron implantation allows for threshold voltage adjustment in the memory cell transistor for the SRAM device. The boron implantation may be performed at an energy level of about 60 KeV so as to achieve an impurity dosage of about 3.times.10.sup.12 atoms/cm.sup.2. After that, the photomask is removed.
Step 8
The oxide layer 11 is then removed as shown in FIG. 1c.
Step 9
A gate oxide layer 17 is next formed over the exposed surface of the N-type substrate 10.
Step 10
A polysilicon gate layer 15 is formed over the surface of the gate oxide layer 17.
Step 11
Boron or phosphorous ions are implanted in the polysilicon gate layer 15 in a further ion implantation procedure.
Step 12
Next, by a high temperature annealing procedure the initial voltage adjustment region 16 is produced beneath the gate oxide layer.
The above generally concludes the process for the fabrication of the twin-well transistor structure for conventional SRAM devices. Conventional SRAM products employ N-type silicon substrate wafers in order to prevent interference otherwise caused by I/O bounces or .alpha. particles. The aim is to establish stability of the data held in the memory cell transistors of the SRAM device. These conventional SRAM devices, fabricated over N-substrate wafers, however, have the following disadvantages.
Firstly, because SRAM IC's are becoming more popular for use in many digital electronics systems such as personal computers, a resultant large market demand has caused a supply shortage in the N-type substrate wafers. Secondly, N-type substrate wafers are more difficult and costly to make than the P-type.